1. Field of the Invention
The present invention generally relates to clock signal regenerating circuits, and more particularly to a clock signal regenerating circuit which generates (extracts) a clock signal from a data signal such as an NRZ (Non-Return to Zero) signal. Further, the present invention is concerned with a load capacitance controlling circuit which controls a voltage-controlled oscillator used for a clock signal regenerating circuit or the like.
The clock signal regenerating technique is needed to realize advanced information communications such as optical fiber communications and high-vision communications. Recently, a PLL (Phase-Locked Loop) circuit operating in the order of giga-heltz has been attracted as a circuit which configures the clock signal regenerating circuit.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional PLL circuit. The PLL circuit shown in FIG. 1 includes an input terminal 1 to which an input signal SIN is applied, an output terminal 2 via which an output signal SOUT is output, a phase/frequency detector (PFD) 3, a charge pump circuit (CP) 4, an amplifier (AMP) 5, a loop filter (LP) 6, and a voltage-controlled oscillator (VCO) 7.
The phase/frequency detector 3 detects the frequency difference between the input signal SIN and the output signal SOUT. The frequency signal is applied to the charge pump circuit 4, which performs a charging or discharging operation on a built-in capacitor. The amplifier 5 amplifies the output signal of the charge pump circuit 4, and results in voltage signals VA and VB. The voltage-controlled oscillator 7 is controlled so that the oscillation frequency of the output signal SOUT can be controlled by the voltage signals VA and VB. In this way, the frequency difference between the input signal SIN and the output signal SOUT is reduced and is made to finally become zero.
In the above PLL circuit, the frequency of the input signal SIN is needed to be close to the oscillation frequency of the voltage-controlled oscillator 7. Hence, if the input signal SIN is a data signal which changes at random, the PLL circuit cannot perform the PLL operation. As a result, it is necessary to modify the PLL circuit in order to apply the PLL circuit to the clock signal regenerating circuit.
The phase/frequency detector 3 simultaneously performs the phase and frequency comparing operations. When there is a frequency difference or a phase difference between the input signal SIN and the output signal SOUT, the phase/frequency detector 3 cannot instantaneously determines whether the difference is a frequency difference or a phase difference. Hence, the PLL circuit has a disadvantage in which pulling-out of the phase is apt to occur. In this regard, the PLL circuit cannot be used as the clock signal regenerating circuit without any modification.